Our software development capability combined with our extensive EO experience presents a powerful capacity to design, develop and deliver complex elements of a PDGS, such as data processors and calibration monitoring facilities.
EarthCARE Instrument Calibration and Monitoring Facility (ICMF) Development
TVUK is part of the EarthCARE ICMF consortium, with responsibility for the implementation of the calibration algorithms for the ATLID (ATmospheric LIDAR), BBR (Broad Band Radiometer) and MSI (Multispectral Imager) instruments.
The largest Earth Explorer mission to date, EarthCARE is a joint venture between ESA and the Japan Aerospace Exploration Agency
(JAXA). The purpose of the mission is to improve weather forecasts and climate predictions by helping to understand the role that clouds and aerosols in the Earth’s atmosphere have in reflecting and trapping solar radiation.
Our primary activities include:
- Analysis of the calibration algorithm documentation,
- Specification of all auxiliary data files to be generated by the ICM
- Generation of the Detailed Processing Models
- Coding of the calibration processing suites
- Definition of the scientific validation strategy for the calibration algorithms for each instrument.
(A)ATSR 4th Reprocessing FAST (From (A)ATSR to SLSTR Tool) Processor Development
Telespazio VEGA UK has had a long involvement with the (A)ATSR instruments; successive members of the same instrument family with the primary objective of measuring Sea Surface Temperature. SLSTR, on board Sentinel-3, is the latest in this line of radiometers that stretch back to ERS-1’s launch in 1991.
We are responsible for the development of the FAST processor; a key element in the processing chain in the (A)ATSR 4th reprocessing activities. Working with the scientific experts, the objective is to reprocess all historical (A)ATSR data into SLSTR-like formatted products, ensuring the compatibility between the operational data from Sentinel-3 and the 20+ year datasets ESA has in its archives.
TVUK will develop the processor capable of generating (A)ATSR L1b data in a format closely resembling that of the SLSTR data products. Activities include the generation of all applicable documentation related to processor design (Architectural Design Documents, I/O Definition documents, Interface Control Documents), implementation of multiple sub-processors, testing, delivery and support.
